The present invention relates to a semiconductor cell layout definition for use in a layout process of a semiconductor integrated circuit and, more particularly, to a semiconductor cell layout definition having a variable transistor width.
Semiconductor integrated circuits are designed and fabricated by first preparing a schematic diagram or hardware description language (HDL) specification of a logical circuit in which functional elements are interconnected to perform a particular logical function. The schematic diagram or HDL specification is then passed to a series of computer aided design tools which assist the logic designer in converting the schematic diagram or HDL specification to an integrated circuit layout definition which can be fabricated.
The design tools synthesize the schematic diagram or HDL specification into cells of a specific cell library. Each cell corresponds to a logical function unit which is implemented by one or more transistors. For example, a typical CMOS two-input AND gate is implemented by six interconnected transistors. A typical cell library may have several identical cells for each logical function unit, with each cell having a different, predetermined output drive strength. The logic designer selects the cells according to the number of loads that are attached to the cell as well as the estimated interconnection required for routing.
The cells in the library are defined by cell library definitions. Each cell library definition includes cell layout definitions and cell characteristics. The layout definition includes a layout pattern of the transistors in the cell, geometry data for the cell's transistors and cell routing data. The cell characteristics include a cell propagation delay and a model of the cell's function. The propagation delay is a function of the internal cell delay and the output loading of the cell.
During logic synthesis, the design tools generate a netlist from the schematic diagram or HDL specification of the selected cells and the interconnections between the cells. The netlist is used to place the selected cells at particular locations on the integrated circuit layout. Once the selected cells have been placed, the interconnections between the cells are routed along predetermined routing layers. The design tools then determine the output loading of each cell as a function of the number of loads attached to each cell, the placement of each cell and the routed interconnections.
A timing analysis tool identifies timing violations between sequential or "clocked" elements and between sequential elements and input/output terminals of the circuit. The time it takes for a signal to travel along a particular path from one sequential element to another depends upon the number of cells in the path, the internal cell delay, the number of loads attached to the cells in the path, the length of the routed interconnections in the path, and the drive strengths of the transistors in the path. A timing violation occurs when a signal does not reach the intended sequential element during the appropriate clock cycle.
A timing violation may be caused by a number of factors. For example, a particular cell may not have a large enough drive strength to drive the number of loads that are attached to that cell. Also, exceptionally long routing paths may cause timing violations. Timing violations are eliminated by making adjustments at each stage in the layout process. For example, an under driven cell may be fixed by changing the logic diagram to include a cell having a larger drive strength. Alternatively, the logic diagram can be changed to divide the loads between one or more redundant cells. An exceptionally long routing path can be corrected by adjusting the placement of the cells or dividing loads between one or more redundant cells.
Once the timing violations have been corrected, the netlist, the cell layout definitions, the placement data and the routing data together form an integrated circuit layout definition which is used to fabricate the integrated circuit.
The overall power consumption of the integrated circuit is often a concern for the logic designer. The power consumption of an integrated circuit can be reduced through transistor downsizing. Cells having excess drive strength are replaced with other cells in the cell library having lower drive strength. Sizing the transistors in this manner requires a cell library with either a large number of drive strengths per cell function for fine granularity of output drive strength, or only a few drive strengths per cell function with large granularity of output drive strength. Also, sizing the transistors in this manner requires a large number of design iterations. Once the schematic diagram or HDL specification has been changed to replace one cell with another, or when the logic synthesis replaces a cell based on layout data, all subsequent steps must be repeated, including logic synthesis, cell placement, routing and timing analysis.